An arrangement of a microcomputer shown in FIG. 5 is disclosed in JP-A-6-250857, which corresponds to U.S. Pat. No. 6,304,957-B1. The microcomputer is arranged by employing a CPU (Central Processing Unit) 11, a program memory 12 constructed of a ROM (Read-Only Memory), a data memory 13 constructed of a RAM (Random Access Memory), an I/O (Input/Output) block (pin) 14, a timing generator (not shown) for generating a CPU switching signal (clock signal) which will be explained later, a data bus 15 for transmitting/receiving data, an address bus 15 for transmitting/receiving an address signal, and a control bus 17 for transmitting/receiving a read signal, and also, another control bus 18 for transmitting/receiving a write signal.
The above-described CPU 11 is provided with two address registers 19 and 20, and two operation registers 21 and 22 in order to pipeline-process, for example, two sorts of tasks (namely, L task and A task) in a time divisional manner and a parallel mode. Since these address registers 19 and 20, and also, these operation registers 21 and 22 are alternately switched in response to a CPU switching signal, this CPU 11 may outwardly function in such a way that two pieces of CPUs are alternately switched.
In this case, both one address register 19 and one operation register 21 constitute registers used for a CPU0 (namely, for L task), whereas both the other address register 20 and the other operation register 22 constitute registers used for another CPU1 (namely, for A task). In response to switching of these address registers 19 and 20, a value (namely, address of instruction which is fetched next time) of a program counter 23 is updated, and thus, an address signal for the CPU0 (for L task) and another address signal for the CPU1 (for A task) are alternately outputted from this program counter 23 to the program memory 12.
Also, an error detecting circuit 24, and an instruction decoder/instruction sequencer 25 are provided in the CPU 11. The error detecting circuit 24 judges a sort of a task, to which an instruction read out from the program memory 12 belongs so as to detect an error contained in this judged task. The instruction decoder/instruction sequencer 25 decodes an instruction which has passed through the error detecting circuit 24. In response to a content of an instruction decoded by this instruction decoder/instruction sequencer 25, a calculation is executed in a calculator (ALU) 26 by employing the operation registers 21 and 22, and either a read signal or a write signal is outputted to the control buses 17 and 18.
On the other hand, both a program area 27 for the CPU0 (for L task), another program area 28 for the CPU1 (for A task), and a table immediate data area 29 have been provided in the program memory 12. In this case, an L task stored in the program area 27 for the CPU0 has been constituted by such a program which has been fix-looped and by which a branch instruction having a risk to be brought into a program runaway is prohibited. As a consequence, when a program of an L task is executed, an execution of an instruction is started from an address “0”, and then, instructions are sequentially executed from an address “1”, via an address “2”, an address “3”, and so on, and thereafter, when the instructions are executed at a predetermined address, the program counter 23 is brought into an overflow state, and then, is returned to the address “0.” Subsequently, the instructions are repeatedly executed in accordance with the above-described address sequence. Also, all of instructions contained in this L task have been fixed to one word.
The L task is suitable to execute a sequential control process operation, and the program for constituting this L task contains a routine for monitoring a runaway (i.e., malfunction) of the A task, and another routine for a backup sequence used to establish a fail safe of the system. Furthermore, this L task is also equipped with a function as a timer by a fixed loop operation. For instance, when either an increment instruction or a decrement instruction is executed, so that the count value thereof is reached to a predetermined preset value, since an interrupt is produced in a process operation of an A task, this L task can realize a constant time process operation equivalent to a timer interrupt.
On the other hand, in the A task, a branch instruction, which is prohibited in the L task, is also allowed, and this A task is suitable for, for example, a complex analyzing process operation/numeral value processing operation. Similar to the above-described L task, all of instructions of this A task have been fixed to one word instruction. Both op-codes and operands (addresses) have been allocated within one word.
Next, a pipeline control system which is employed by the microcomputer having the above-explained arrangement will now be explained with reference to FIG. 6. This pipeline has been arranged as three stages of pipelines which are made of, for example, an instruction fetch stage, an instruction decode stage, and an instruction execute stage, and has been designed in such a manner that all of these instructions can be processed without any delay by the three stages of pipelines. Each of these three stages is executed within one cycle, and thus, one instruction is executed in three cycles. However, three instructions are processed in a parallel mode by the stages of pipelines, which may outwardly be equivalent to such a fact that one instruction is executed within one cycle.
A time required for one cycle (each stage) has been defined by a CPU switching signal (clock signal). As to this CPU switching signal, a time “TLo” of a low level is equal to a time “THi” of a high level. In the low level period, an instruction fetch of the CPU0 (L task) is executed, whereas in the high level period, and an instruction fetch of the CPU1 (A task) is executed, so that both the program of the CPU0 (L task) and the program of the CPU1 (A task) are pipeline-processed in a parallel mode in such a time divisional ratio of 1:1.
In addition, when the CPU1 fetches a branch instruction contained in the program of the A task, in order to fetch an instruction of a branch destination address in the next instruction fetch stage of the A task into which this fetched branch instruction is contained, the CPU 1 has been arranged in such a manner that the branch destination address is set in the instruction decode stage. FIG. 6 represents process timing in such a case that while a pipeline process operation is carried out, an instruction of the CPU1 at an address (Y+1) corresponds to a branch instruction (JMP) to an address (YY).
The CPU 11 has been equipped with the plurality of address registers 19 and 20, and the plurality of operation registers 21 and 22. These plural address registers 19 and 20 sequentially set different instruction addresses to the program counter 23. The plural operation registers 21 and 22 sequentially set instructions decoded by the instruction decoder/instruction sequencer 25 to the calculator 26. The CPU 11 has been arranged so as to be capable of pipeline-processing the plural programs 27 and 28 stored in the program memory 12 by sequentially switching the plural address registers 19 and 20, and the plural operation registers 21 and 22.
As previously described, in the microcomputer, since the execution of the branch instruction is prohibited (namely, description of branch instruction in program is prohibited) in the L task, the count value of the program counter 23 is always incremented by “1” (in this case, count value of program counter 23 has been set in above-described manner irrespective of byte number of one instruction), and thus, the L task can realize the runaway monitoring process operation on the side of the A task, and the timer function utilizing the count value of the program counter 23.
However, since such a restriction for prohibiting the branch instruction is given to the side of the L task, the branching process operation cannot be executed on the side of the L task. As a result, there is such a problem that, for instance, a conditional control flow cannot be executed on the L task side, while this conditional control flow selects as to whether or not a predetermined calculating process operation can be carried out in response to a result of executing a predetermined condition judgement.
Further, in microcomputers, there are such application programs capable of executing process operations in a time constant manner by utilizing interrupt process operations. For instance, in communication process operations, exclusively-used communication control blocks are mounted in order to secure time constant systems of communication speeds. In this connection, the Inventors of the present invention have supposed that, instead of the employment of the above-explained communication control blocks, desirable communications are realized by employing both a timer interrupt process operation and a software process operation. If the desirable communications can be realized by these timer interrupt and software process operations, then the above-described communication control blocks are no longer mounted and microcomputers can be constructed in low cost.
However, in this case, there is a problem how to realize the above-explained time constant process operation. That is to say, the timer interrupt must be executed without any shift of even one cycle. If the timer interrupt is shifted only for even one cycle, then an adverse influence may be produced as a communication speed error. On the other hand, since execution times of various sorts of instructions which are executed by a CPU may be different from each other, if an interrupt request is issued in a half way while such an instruction whose execution time is longer than that of another instruction is executed, there are some cases that a commencement of an interrupt process operation is held.
In other words, as indicated in FIG. 14A, for instance, while all of instructions are executed in the unit of one cycle, if an interrupt request is issued in such a case that a value (instruction fetch address) of a program counter is sequentially incremented by “1”, then this interrupt request is not held, but an interrupt process operation is immediately commenced from a head address “200.” To the contrary, as shown in FIG. 14B, if an interrupt request is issued in a half way while an instruction, whose execution time is equal to two cycles, is carried out, then this interrupt request is held for one cycle, so that start timing of the interrupt process operation is delayed.
For example, such a programmable controller is disclosed in JP-A-2001-265412, which corresponds to U.S. Pat. No. 6,880,029. That is, in this programmable controller, a normal process operation (user program executing process operation, I/O refreshing process operation) is executed in a cyclic manner, and also, an interrupt trigger is generated in a predetermined time period. Then, the execution of the user program executing process operation is interrupted at the timing when this interrupt trigger is generated, and a peripheral service process operation is carried out only by a determined amount.
However, in accordance with the conventional technique, in such a case that the interrupt process operation is held, it is not possible to avoid such a fact that the execution start timing of the peripheral service processing operation is shifted. In other words, the conventional technique never supposes, or expects such a strict time management capable of avoiding that the execution start timing is shifted by one cycle.
Furthermore, as systems for controlling condition branches of programs in CPUs (processors), conventionally, the below-mentioned two systems have been proposed:
(i) A control system in which, while a conditional branch instruction and the like are contained in an instruction set, when a condition can be established, a process operation jumps to a designated address.
(ii) A system in which, while a skip instruction is contained in an instruction set, either one instruction or a plurality of continuous instructions are invalidated which are provided immediately after the skip instruction. Such a technical idea for causing an instruction to be brought into a non-operation state when a process operation skips has been described in, for instance, JP-A-61-221939.
In any of the above-described condition branch control systems (i) and (ii), a total execution cycle number when a condition can be established is different from a total execution cycle number when a condition cannot be established. As a result, there is such a problem that in a program and a system thereof in which execution timing of an instruction is important, such instructions after a branching process operation (namely, after skipping process operation in combination with non-operation treatment of instruction) cannot be executed at the same cycle timing.
For example, in the above-described condition branch control system (ii), the above-described problem corresponds to a load/store instruction having such a data size which exceeds a bus width, namely, a plurality of cycles are required so as to execute such a load/store instruction, which may cause the above-explained problem.